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? 2004 microchip technology inc. ds21191m-page 1 24aa128/24lc128/24fc128 device selection table features ? low-power cmos technology: - maximum write current 3 ma at 5.5v - maximum read current 400 a at 5.5v - standby current 100 na typical at 5.5v 2-wire serial interface bus, i 2 c? compatible cascadable for up to eight devices self-timed erase/write cycle 64-byte page write mode available 5 ms max write cycle time hardware write-protect for entire array output slope control to eliminate ground bounce schmitt trigger inputs for noise suppression 1,000,000 erase/write cycles electrostatic discharge protection > 4000v data retention > 200 years 8-pin pdip, soic, tssop, msop and dfn packages, 14-lead tssop package standard and pb-free finishes available temperature ranges: description the microchip technology inc. 24aa128/24lc128/ 24fc128 (24xx128*) is a 16k x 8 (128 kbit) serial electrically erasable prom (eeprom), capable of operation across a broad voltage range (1.8v to 5.5v). it has been developed for advanced, low-power applications such as personal communications or data acquisition. this device also has a page write capabil- ity of up to 64 bytes of data. this device is capable of both random and sequential reads up to the 128k boundary. functional address lines allow up to eight devices on the same bus, for up to 1 mbit address space. this device is available in the standard 8-pin plastic dip, soic (150 and 208 mil), tssop, msop, dfn and 14-lead tssop packages. block diagram package types *24xx128 is used in this document as a generic part number for the 24aa128/24lc128/24fc128 devices. part number v cc range max. clock frequency temp. ranges 24aa128 1.8-5.5v 400 khz (1) i 24lc128 2.5-5.5v 400 khz i, e 24fc128 1.8-5.5v 1 mhz (2) i note 1: 100 khz for v cc < 2.5v. 2: 400 khz for v cc < 2.5v. - industrial (i): -40 c to +85 c - automotive (e): -40 c to +125 c hv generator eeprom array page latches ydec xdec sense amp. r/w control m emory c ontrol l ogic i/o c ontrol l ogic i/o a0 a1 a2 sda scl v cc v ss wp a0 a1 a2 v ss v cc wp scl sda 1 2 3 4 8 7 6 5 24xx128 pdip/soic tssop/msop * a0 a1 a2 v ss 1 2 3 4 8 7 6 5 v cc wp scl sda tssop 24xx128 dfn a0 a1 a2 v ss wp scl sda 24xx128 5 6 7 8 4 3 2 1 v cc nc a0 a1 nc a2 v ss nc nc v cc wp nc scl sda nc 24xx128 1 2 3 4 14 13 12 11 5 10 6 9 7 8 note: * pins a0 and a1 are no-connects for the msop package only. 128k i 2 c ? cmos serial eeprom
24aa128/24lc128/24fc128 ds21191m-page 2 ? 2004 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................6.5v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.6v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied ......................................................................................... .......-40c to +125c esd protection on all pins ............................................................................................................................... ....................... 4kv table 1-1: dc characteristics ? notice : stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics electrical characteristics: industrial (i): v cc = +1.8v to 5.5v t a = -40c to +85c automotive (e): v cc = +2.5v to 5.5v t a = -40c to 125c param. no. sym. characteristic min. max. units conditions d1 ? a0, a1, a2, scl, sda, and wp pins: ???? d2 v ih high-level input voltage 0.7 v cc ?v? d3 v il low-level input voltage ? 0.3 v cc 0.2 v cc v v v cc 2.5v v cc < 2.5v d4 v hys hysteresis of schmitt trigger inputs (sda, scl pins) 0.05 v cc ?vv cc 2.5v (note 1) d5 v ol low-level output voltage ? 0.40 v i ol = 3.0 ma @ v cc = 4.5v i ol = 2.1 ma @ v cc = 2.5v d6 i li input leakage current ? 1 av in = v ss or v cc , wp = v ss v in = v ss or v cc , wp = v cc d7 i lo output leakage current ? 1 av out = v ss or v cc d8 c in , c out pin capacitance (all inputs/outputs) ?10pfv cc = 5.0v (note 1) t a = 25c, f c = 1 mhz d9 i cc read operating current ? 400 av cc = 5.5v, scl = 400 khz i cc write ? 3 ma v cc = 5.5v d10 i ccs standby current ? 1 at a = -40c to +85c scl = sda = v cc = 5.5v a0, a1, a2, wp = v ss ?5 at a = -40c to 125c scl = sda = v cc = 5.5v a0, a1, a2, wp = v ss note 1: this parameter is periodically sampled and not 100% tested.
? 2004 microchip technology inc. ds21191m-page 3 24aa128/24lc128/24fc128 table 1-2: ac characteristics ac characteristics electrical characteristics: industrial (i): v cc = +1.8v to 5.5v t a = -40c to +85c automotive (e): v cc = +2.5v to 5.5v t a = -40c to 125c param. no. sym. characteristic min. max. units conditions 1f clk clock frequency ? ? ? ? 100 400 400 1000 khz 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc < 2.5v 24fc128 2.5v v cc 5.5v 24fc128 2t high clock high time 4000 600 600 500 ? ? ? ? ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc < 2.5v 24fc128 2.5v v cc 5.5v 24fc128 3t low clock low time 4700 1300 1300 500 ? ? ? ? ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc < 2.5v 24fc128 2.5v v cc 5.5v 24fc128 4t r sda and scl rise time (note 1) ? ? ? 1000 300 300 ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc 5.5v 24fc128 5t f sda and scl fall time (note 1) ? ? 300 100 ns all except, 24fc128 1.8v v cc 5.5v 24fc128 6t hd : st a start condition hold time 4000 600 600 250 ? ? ? ? ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc < 2.5v 24fc128 2.5v v cc 5.5v 24fc128 7t su : st a start condition setup time 4700 600 600 250 ? ? ? ? ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc < 2.5v 24fc128 2.5v v cc 5.5v 24fc128 8t hd : da t data input hold time 0 ? ns (note 2) 9t su : da t data input setup time 250 100 100 ? ? ? ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc 5.5v 24fc128 10 t su : st o stop condition setup time 4000 600 600 250 ? ? ? ? ns 1.8 v v cc < 2.5v 2.5 v v cc 5.5v 1.8v v cc < 2.5v 24fc128 2.5 v v cc 5.5v 24fc128 11 t su : wp wp setup time 4000 600 600 ? ? ? ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc 5.5v 24fc128 note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs, which provide improved noise spike suppression. this eliminates the need for a t i specification for standard operation. 4: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model, which can be obtained from microchip?s web site: www.microchip.com.
24aa128/24lc128/24fc128 ds21191m-page 4 ? 2004 microchip technology inc. figure 1-1: bus timing data 12 t hd : wp wp hold time 4700 1300 1300 ? ? ? ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc 5.5v 24fc128 13 t aa output valid from clock (note 2) ? ? ? ? 3500 900 900 400 ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc < 2.5v 24fc128 2.5v v cc 5.5v 24fc128 14 t buf bus free time: time the bus must be free before a new transmission can start 4700 1300 1300 500 ? ? ? ? ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc < 2.5v 24fc128 2.5v v cc 5.5v 24fc128 15 t of output fall time from v ih minimum to v il maximum c b 100 pf 10 + 0.1c b 250 250 ns all except, 24fc128 (note 1) 24fc128 (note 1) 16 t sp input filter spike suppression (sda and scl pins) ? 50 ns all except, 24fc128 (notes 1 and 3) 17 t wc write cycle time (byte or page) ?5ms? 18 ? endurance 1,000,000 ? cycles 25c (note 4) table 1-2: ac characteristics (continued) ac characteristics electrical characteristics: industrial (i): v cc = +1.8v to 5.5v t a = -40c to +85c automotive (e): v cc = +2.5v to 5.5v t a = -40c to 125c param. no. sym. characteristic min. max. units conditions note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs, which provide improved noise spike suppression. this eliminates the need for a t i specification for standard operation. 4: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model, which can be obtained from microchip?s web site: www.microchip.com. (unprotected) (protected) scl sda in sda out wp 5 7 6 16 3 2 89 13 d4 4 10 11 12 14
? 2004 microchip technology inc. ds21191m-page 5 24aa128/24lc128/24fc128 2.0 pin descriptions the descriptions of the pins are listed in table 2-1. table 2-1: pin function table 2.1 a0, a1, a2 chip address inputs the a0, a1 and a2 inputs are used by the 24xx128 for multiple device operations. the levels on these inputs are compared with the corresponding bits in the slave address. the chip is selected if the compare is true. for the msop package only, pins a0 and a1 are not connected. up to eight devices (two for the msop package) may be connected to the same bus by using different chip select bit combinations. if these pins are left uncon- nected, the inputs will be pulled down internally to v ss . if they are tied to v cc or driven high, the internal pull-down circuitry is disabled. in most applications, the chip address inputs a0, a1, and a2 are hard-wired to logic ? 0 ? or logic ? 1 ?. for applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ? 0 ? or logic ? 1 ? before normal device operation can proceed. 2.2 serial data (sda) this is a bidirectional pin used to transfer addresses and data into and out of the device. it is an open drain terminal. therefore, the sda bus requires a pull-up resistor to v cc (typical 10 k ? for 100 khz, 2 k ? for 400khz and 1mhz). for normal data transfer, sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 2.3 serial clock (scl) this input is used to synchronize the data transfer to and from the device. 2.4 write-protect (wp) this pin can be connected to either v ss , v cc or left floating. internal pull-down circuitry on this pin will keep the device in the unprotected state if left floating. if tied to v ss or left floating, normal memory operation is enabled (read/write the entire memory 0000-3fff). if tied to v cc , write operations are inhibited. read operations are not affected. 3.0 functional description the 24xx128 supports a bidirectional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. the bus must be controlled by a master device which generates the serial clock (scl), controls the bus access and generates the start and stop conditions while the 24xx128 works as a slave. both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. name 8-pin pdip 8-pin soic 8-pin tssop 14-pin tssop 8-pin msop 8-pin dfn function a0 1 1 1 1 ? 1 user configurable chip select a1 2 2 2 2 ? 2 user configurable chip select (nc) ? ? ? 3, 4, 5 1, 2 ? not connected a2 3 3 3 6 3 3 user configurable chip select v ss 4 4 4 7 4 4 ground sda 5 5 5 8 5 5 serial data scl 6 6 6 9 6 6 serial clock (nc) ? ? ? 10, 11,12 ? ? not connected wp 7 7 7 13 7 7 write-protect input v cc 8 8 8 14 8 8 +1.8v to 5.5v (24aa128) +2.5v to 5.5v (24lc128) +1.8v to 5.5v (24fc128)
24aa128/24lc128/24fc128 ds21191m-page 6 ? 2004 microchip technology inc. 4.0 bus characteristics the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 4-1). 4.1 bus not busy (a) both data and clock lines remain high. 4.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 4.3 stop data transfer (c) a low-to-high transition of the sda line, while the clock (scl) is high, determines a stop condition. all operations must end with a stop condition. 4.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one bit of data per clock pulse. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device. 4.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. the master device must generate an extra clock pulse, which is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (24xx128) will leave the data line high to enable the master to generate the stop condition. figure 4-1: data transfer sequence on the serial bus figure 4-2: acknowledge timing note: the 24xx128 does not generate any acknowledge bits if an internal programming cycle is in progress. address or acknowledge valid data allowed to change stop condition start condition scl sda (a) (b) (d) (d) (c) (a) scl 9 8 7 6 5 4 3 2 1123 transmitter must release the sda line at this point, allowing the receiver to pull the sda line low to acknowledge the previous eight bits of data. receiver must release the sda line at this point so the transmitter can continue sending data. data from transmitter sda acknowledge bit data from transmitter
? 2004 microchip technology inc. ds21191m-page 7 24aa128/24lc128/24fc128 5.0 device addressing a control byte is the first byte received following the start condition from the master device (figure 5-1). the control byte consists of a 4-bit control code. for the 24xx128, this is set as ? 1010 ? binary for read and write operations. the next three bits of the control byte are the chip select bits (a2, a1, a0). the chip select bits allow the use of up to eight 24xx128 devices on the same bus and are used to select which device is accessed. the chip select bits in the control byte must correspond to the logic levels on the corresponding a2, a1 and a0 pins for the device to respond. these bits are, in effect, the three most significant bits of the word address. for the msop package, the a0 and a1 pins are not connected. during device addressing, the a0 and a1 chip select bits (figures 5-1 and 5-2) should be set to ? 0 ?. only two 24xx128 msop packages can be connected to the same bus. the last bit of the control byte defines the operation to be performed. when set to a one, a read operation is selected. when set to a zero, a write operation is selected. the next two bytes received define the address of the first data byte (figure 5-2). because only a13?a0 are used, the upper two address bits are ?don?t care? bits. the upper address bits are transferred first, followed by the less significant bits. following the start condition, the 24xx128 monitors the sda bus checking the device type identifier being transmitted. upon receiving a ? 1010 ? code and appropriate device select bits, the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the 24xx128 will select a read or write operation. figure 5-1: control byte format 5.1 contiguous addressing across multiple devices the chip select bits a2, a1,and a0 can be used to expand the contiguous address space for up to 1 mbit by adding up to eight 24xx128s on the same bus. in this case, software can use a0 of the control byte as address bit a14; a1 as address bit a15; and a2 as address bit a16. it is not possible to sequentially read across device boundaries. for the msop package, up to two 24xx128 devices can be added for up to 256 kbit of address space. in this case, software can use a2 of the control byte as address bit a16. bits a0 (a14) and a1 (a15) of the control byte must always be set to logic ? 0 ? for the msop. figure 5-2: address sequence bit assignments 1 0 1 0 a2 a1 a0 sack r/w control code chip select bits slave address acknowledge bit start bit read/write bit 1010 a 2 a 1 a 0 r/w xx a 11 a 10 a 9 a 7 a 0 a 8 a 12 control byte address high byte address low byte control code chip select bits x = don?t care bit a 13
24aa128/24lc128/24fc128 ds21191m-page 8 ? 2004 microchip technology inc. 6.0 write operations 6.1 byte write following the start condition from the master, the control code (four bits), the chip select (three bits) and the r/w bit (which is a logic low) are clocked onto the bus by the master transmitter. this indicates to the addressed slave receiver that the address high byte will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24xx128. the next byte is the least significant address byte. after receiving another acknowledge signal from the 24xx128, the master device will transmit the data word to be written into the addressed memory location. the 24xx128 acknowl- edges again and the master generates a stop condition. this initiates the internal write cycle and during this time, the 24xx128 will not generate acknowledge signals (figure 6-1). if an attempt is made to write to the array with the wp pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written, and the device will immediately accept a new command. after a byte write command, the internal address counter will point to the address location following the one that was just written. 6.2 page write the write control byte, word address, and the first data byte are transmitted to the 24xx128 in much the same way as in a byte write. the exception is that instead of generating a stop condition, the master transmits up to 63 additional bytes, which are temporarily stored in the on-chip page buffer, and will be written into memory once the master has transmitted a stop condition. upon receipt of each word, the six lower address pointer bits are internally incremented by ? 1 ?. if the master should transmit more than 64 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be over- written. as with the byte write operation, once the stop condition is received, an internal write cycle will begin (figure 6-2). if an attempt is made to write to the array with the wp pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command. 6.3 write-protection the wp pin allows the user to write-protect the entire array (0000-3fff) when the pin is tied to v cc . if tied to v ss or left floating, the write protection is disabled. the wp pin is sampled at the stop bit for every write command (figure 1-1). toggling the wp pin after the stop bit will have no effect on the execution of the write cycle. figure 6-1: byte write figure 6-2: page write note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or ?page size?) and end at addresses that are integer multiples of [page size - 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (over- writing data previously stored there), instead of being written to the next page, as might be expected. it is, therefore, necessary for the applica- tion software to prevent page write operations that would attempt to cross a page boundary. xx bus activity master sda line bus activity s t a r t control byte address high byte address low byte data s t o p a c k a c k a c k a c k x = don?t care bit s1010 0 a 2 a 1 a 0 p xx bus activity master sda line bus activity s t a r t control byte address high byte address low byte data byte 0 s t o p a c k a c k a c k a c k data byte 63 a c k x = don?t care bit s1010 0 a 2 a 1 a 0 p
? 2004 microchip technology inc. ds21191m-page 9 24aa128/24lc128/24fc128 7.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition, followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, then no ack will be returned. if no ack is returned, the start bit and control byte must be resent. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 7-1 for flow diagram. figure 7-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0 )? next operation no yes
24aa128/24lc128/24fc128 ds21191m-page 10 ? 2004 microchip technology inc. 8.0 read operation read operations are initiated in much the same way as write operations with the exception that the r/w bit of the control byte is set to ? 1 ?. there are three basic types of read operations: current address read, random read and sequential read. 8.1 current address read the 24xx128 contains an address counter that main- tains the address of the last word accessed, internally incremented by ? 1 ?. therefore, if the previous read access was to address ? n ? ( n is any legal address), the next current address read operation would access data from address n + 1 . upon receipt of the control byte with r/w bit set to ? 1 ?, the 24xx128 issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 24xx128 discontinues transmission (figure 8-1). figure 8-1: current address read 8.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, the word address must first be set. this is done by sending the word address to the 24xx128 as part of a write operation (r/w bit set to ? 0 ? ). once the word address is sent, the master gener- ates a start condition following the acknowledge. this terminates the write operation, but not before the inter- nal address pointer is set. the master then issues the control byte again, but with the r/w bit set to a ? 1 ?. the 24xx128 will then issue an acknowledge and transmit the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition, which causes the 24xx128 to discontinue transmission (figure 8-2). after a random read command, the internal address counter will point to the address location following the one that was just read. 8.3 sequential read sequential reads are initiated in the same way as a random read except that after the 24xx128 transmits the first data byte, the master issues an acknowledge as opposed to the stop condition used in a random read. this acknowledge directs the 24xx128 to transmit the next sequentially addressed 8-bit word (figure 8-3). following the final byte transmitted to the master, the master will not generate an acknowledge but will generate a stop condition. to provide sequential reads, the 24xx128 contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. the internal address pointer will automatically roll over from address 3fff to address 0000 if the master acknowledges the byte received from the array address 3fff. figure 8-2: random read figure 8-3: sequential read bus activity master sda line bus activity p s s t o p control byte s t a r t data a c k n o a c k 11 00 aaa 1 byte 210 xx bus activity master sda line bus activity a c k n o a c k a c k a c k a c k s t o p s t a r t control byte address high byte address low byte control byte data byte s t a r t x = don?t care bit s1 01 0 aaa 0 210 s1010 aaa 1 210 p bus activity master sda line bus activity control byte data (n) data (n + 1) data (n + 2) data (n + x) n o a c k a c k a c k a c k a c k s t o p p
? 2004 microchip technology inc. ds21191m-page 11 24aa128/24lc128/24fc128 9.0 packaging information 9.1 package marking information xxxxxxxx t/xxxnnn yyww 8-lead pdip (300 mil) example: 8-lead tssop example: 8-lead soic (150 mil) example: xxxxxxxx t/xxyyww nnn xxxx tyww nnn 8-lead soic (208 mil) example: 24lc128 0310017 i/sm 24aa128 i/p017 0310 xxxxxxxx yywwnnn t/xxxxxx 24lc128 i/sn0310 017 4lc i301 017
24aa128/24lc128/24fc128 ds21191m-page 12 ? 2004 microchip technology inc. package marking information (continued) 14-lead tssop example : xxxxxxxt yyww nnn 8-lead msop example: xxxxxt ywwnnn 4l128i 101017 24lc128i 0110 017 8-lead dfn-s example : xxxxxxx t/xxxxx yyww 24lc128 i/mf yyww nnn nnn tssop package codes msop package codes part no. std pb-free std pb-free 24aa128 4ac g4ac 4a128 g4ac 24lc128 4lc g4lc 4l128 g4lc 24fc128 4fc g4fc 4f128 g4fc legend: xx...x customer specific information* t temperature grade (i, e) y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note :in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard device marking consists of microchip part number, year code, week code, and traceability code. for device marking beyond this, certain price adders apply. please check with your microchip sales office.
? 2004 microchip technology inc. ds21191m-page 13 24aa128/24lc128/24fc128 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
24aa128/24lc128/24fc128 ds21191m-page 14 ? 2004 microchip technology inc. 8-lead plastic small outline (sn) ? narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
? 2004 microchip technology inc. ds21191m-page 15 24aa128/24lc128/24fc128 8-lead plastic small outline (sm) ? medium, 208 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.43 0.36 .020 .017 .014 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.64 0.51 .030 .025 .020 l foot length 5.33 5.21 5.13 .210 .205 .202 d overall length 5.38 5.28 5.11 .212 .208 .201 e1 molded package width 8.26 7.95 7.62 .325 .313 .300 e overall width 0.25 0.13 0.05 .010 .005 .002 a1 standoff 1.98 .078 a2 molded package thickness 2.03 .080 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 a a1 l c 2 1 d n p b e e1 .070 .075 .069 .074 1.78 1.75 1.97 1.88 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. drawing no. c04-056 significant characteristic
24aa128/24lc128/24fc128 ds21191m-page 16 ? 2004 microchip technology inc. 8-lead plastic thin shrink small outline (st) ? 4.4 mm (tssop) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 3.10 3.00 2.90 .122 .118 .114 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 .043 a overall height 0.65 .026 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters* inches units a2 a a1 l c 1 2 d n p b e e1 foot angle 048048 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005? (0.127mm) per side. jedec equivalent: mo-153 drawing no. c04-086 significant characteristic
? 2004 microchip technology inc. ds21191m-page 17 24aa128/24lc128/24fc128 14-lead plastic thin shrink small outline (st) ? 4.4 mm (tssop) 8 4 0 8 4 0 foot angle 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 5.10 5.00 4.90 .201 .197 .193 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 .043 a overall height 0.65 .026 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters* inches units l c 2 1 d n b p e1 e a2 a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005? (0.127mm) per side. jedec equivalent: mo-153 drawing no. c04-087 significant characteristic
24aa128/24lc128/24fc128 ds21191m-page 18 ? 2004 microchip technology inc. 8-lead plastic micro small outline package (ms) (msop) d a a1 l c (f) a2 e1 e p b n 1 2 dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not .037 ref f footprint (reference) exceed .010" (0.254mm) per side. notes: drawing no. c04-111 *controlling parameter mold draft angle top mold draft angle bottom foot angle lead width lead thickness c b .003 .009 .006 .012 dimension limits overall height molded package thickness molded package width overall length foot length standoff overall width number of pins pitch a l e1 d a1 e a2 .016 .024 .118 bsc .118 bsc .000 .030 .193 typ. .033 min p n units .026 bsc nom 8 inches 0.95 ref - - .009 .016 0.08 0.22 0 0.23 0.40 8 millimeters* 0.65 bsc 0.85 3.00 bsc 3.00 bsc 0.60 4.90 bsc .043 .031 .037 .006 0.40 0.00 0.75 min max nom 1.10 0.80 0.15 0.95 max 8 -- - 15 5 - 15 5 - jedec equivalent: mo-187 0 - 8 5 5 - - 15 15 - - - -
? 2004 microchip technology inc. ds21191m-page 19 24aa128/24lc128/24fc128 8-lead plastic dual flat no lead package (mf) 6x5 mm body (dfn-s) nom .050 bsc inches .194 bsc .184 bsc .226 bsc .236 bsc .008 ref. d overall width jedec equivalent: pending notes: drawing no. c04-113 molded package width lead width *controlling parameter mold draft angle top tie bar width lead length r b l d1 .014 .020 dimension limits molded package thickness pitch overall height overall length molded package length base thickness standoff number of pins a3 e1 e a2 a1 a .000 units n p min top view 12 a2 a 5.99 bsc .019 12 .030 .014 .016 .024 0.35 0.50 .356 0.40 0.60 5.74 bsc 12 0.47 0.75 millimeters* .039 .002 .031 .026 .0004 .033 0.00 8 max min 1.27 bsc 0.20 ref. 4.92 bsc 4.67 bsc 0.85 0.01 0.65 0.80 0.05 1.00 max nom 8 bottom view n e e1 pin 1 p b exposed pad length e2 exposed pad width d2 .085 .091 .097 2.16 2.31 2.46 .152 .158 .163 3.85 4.00 4.15 exposed metal pads d2 e2 a1 a3 l id d1 d r dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per si de.
24aa128/24lc128/24fc128 ds21191m-page 20 ? 2004 microchip technology inc. appendix a: revision history revision l corrections to section 1.0, electrical characteristics. revision m added 1.8v 400 khz option for 24fc128.
? 2004 microchip technology inc. ds21191m-page 21 24aa128/24lc128/24fc128 on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is available by using an ftp service to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive the most current upgrade kits. the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. 042003
24aa128/24lc128/24fc128 ds21191m-page 22 ? 2004 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21191m 24aa128/24lc128/24fc128 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2004 microchip technology inc. ds21191m-page23 24aa128/24lc128/24fc128 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . sales and support data sheets products supported by a preliminary data sheet may have an e rrata sheet describing minor operational differences and recom- mended workarounds. to determine if an erra ta sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. part no. x /xx package temperature range device device: 24aa128: 128 kbit 1.8v i 2 c serial eeprom 24aa128t: 128 kbit 1.8v i 2 c serial eeprom (tape and reel) 24lc128: 128 kbit 2.5v i 2 c serial eeprom 24lc128t: 128 kbit 2.5v i 2 c serial eeprom (tape and reel) 24fc128: 128 kbit high speed i 2 c serial eeprom 24fc128t: 128 kbit high speed i 2 c serial eeprom (tape and reel) temperature range: i= -40 c to +85 c e= -40 c to +125 c package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead sm = plastic soic (208 mil body), 8-lead st = plastic tssop (4.4 mm), 8-lead st14 = plastic tssop (4.4 mm), 14-lead mf = dual, flat, no lead (dfn)(6x5 mm body), 8-lead ms = plastic micro small outline (msop), 8-lead lead finish blank= standard 63%/37% sn/pb g = pb-free (pure matte sn) examples: a) 24aa128-i/p: industrial temp., 1.8v, pdip package. b) 24aa128t-i/sn: tape and reel, industrial temp., 1.8v, soic package. c) 24aa128-i/st: industrial temp., 1.8v, tssop package. d) 24aa128-i/ms: industrial temp., 1.8v, msop package. e) 24lc128-e/p: extended temp., 2.5v, pdip package. f) 24lc128-i/sn: industrial temp., 2.5v, soic package. g) 24lc128t-i/sn: tape and reel, industrial temp., 2.5v, soic package. h) 24lc128-i/ms: industrial temp., 2.5v, msop package. i) 24fc128-i/p: industrial temp., 1.8v, high speed, pdip package. j) 24fc128-i/sn: industrial temp., 1.8v, high speed, soic package. k) 24fc128t-i/sn: tape and reel, industrial temp., 1.8v, high speed, soic package l) 24lc128t-i/stg: industrial temp., 2.5v, tssop package, tape & reel, pb-free m) 24lc128-i/pg: industrial temp., 2.5v, pdip package, pb-free x lead finish
24aa128/24lc128/24fc128 ds21191m-page24 ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. ds21191m-page 25 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of micr ochip?s products as critical components in life support syst ems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or ot herwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel and total endurance ar e trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2004, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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